Sonne

This project was initially published and maintained on Github a few years ago. I refer you to the download package if you are interested in details.

The goal was to build a working, practical CPU using through-hole technology and 74HC style components as much as possible. The design of the instruction set has traces in my misguided mind that go back at least a decade or so.

Well, actually, it goes back to when I was a teenager and got interested in electronics wanting to build my own computer hardware.

With only a little bit of handwaving (fat EEPROM for ALU hint-hint, four-layer PCB cough…), I could have built exactly this back in the 80ies for not even that much money with the previous generation of those same chips (74LS). They still cost well under a dollar at unit price, mostly.

What does it look like?

The CPU board looks like this (this is an older revision, notice the wire patch):

These plastic spacers go between the CPU board and the IO board. The distance/length of the spacer part (without the protruding thread) is 2 cm.

Both modules go together like so:

The assembled development kit i.e. hardware portion of this project:

Demo Video

This demonstration video shows the Sonne controller board with the I/O-board stacked on top of it.

In the video, the computer loads a program for multiplying 7 by 13 from a serial EEPROM and executes it in two step process.

Step 1: The controller’s tiny “firmware” is stored in a parallel EEPROM (large chip top-center marked “App”) that is mapped into the CPU’s address space. When reset is applied, an initial “boot loader” in the firmware is started.

Step 2: The boot loader talks to the SPI interface of the IO board to load the multiplication routine from a serial EEPROM (little square chip bottom center left on the IO-board), just like a “real” micro-controller should! Something that I have never gotten around to do, is write code to load this from the SD-card interface I’ve provided on the IO board, although I already have working code for this from my earlier 16-bit CPU which I could port.

Both programs are written in the CPU’s native assembly language. The object code is generated by a small assembler I wrote for this project. The multiplication routine then takes over, computes the result and displays it on the I/O boards 7-segment display.

What is interesting about this is that none of the electronics components used is an Arduino or micro-controller or CPU – the circuit is the CPU described in this project.

The multiplication code that ran was the following:

; This file assembles with assem.c
; Write object code into SPI EEPROM on IO board


;G3 low result
;G4 high result

;L1 lsb
;L2 msb
;L3 loop counter
;L4 multiplier
;L5 temp

RAM

LA 7 aG1p  ;G1 multiplicand
LA 13 aG2p ;G2 multiplier

aG1g aL1p     ; initialize copy multiplicand
LA 0 aL2p     ; clear msb
LA 8 aL3p     ; initialize loop counter, 8 bits
LID

@loop
LB 1, aL1g, LF AND, LE >skip   ; add multiplier if low order lsb set
aG2g bL2g LF ADD, FB bL2p
LID

@skip ; shift right
LB 1 aL2g, LF AND, FB, bL5p  ; check if high order lsb set
aL1g, LF SRA, FB bL1p
aL2g, LF SRA, FB bL2p
aL5g, LF IDA, LE >done
LA 80h, bL1g, LF IOR, FA aL1p
LID

@done
aL3g, LF IDA-1 FA, aL3p
LF IDA, LT <loop

LD 0
aL1g, LF IDA, FP     ; Display result 7*13=91 = 5Bh
LD 0001.0000b
LD 0.
@STOP1 LJ <STOP1.

If you stop and think, although it’s such a puny project, I still think it’s cool and creative: The code above is in an assembly language I had to come up with, for an instruction set and architecture that did not exist before, which runs on a CPU that only exists once, and for which I had to write an assembler because there wasn’t one.

I’ve presented this at CrashSpace in Culver City (Los Angeles) on October 10th, 2023 and donated my build of the controller, including two spare PCBs. So if you’re in the area and would like to work on it, ask the staff if it’s still available.

There is now a successor model (see “Myth” in the Embedded section of my website), and I probably won’t pursue Sonne further. But it was a fascinating journey and I gained a few experience points.

Earlier Revisions

The download package only includes the most recent Git commit. A feature I started out with but abandoned, was an implicit segmentation of the page in 128 byte code (7-bit PC), 64 byte data, and 64 byte local storage. All of these segments could be bank-switched using dedicated page index registers. So by sacrificing addressing/offset range, you could use certain address bit combinations to address memory spaces that behaved in a different way semantically without overhead. I still think that might be worth pursuing to extend the useful range of 8-bit machines.

I think there is even a working Verilog implementation of the CPU for the DE1/SOC board by Terasic in there which also passes the multiplication routine and outputs to 7-Segment display, but can’t remember.

Downloads

I’ve put up for downloading the project files , including the KiCad PCB files I used to order the working PCB from JLCPCB.